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Features
* Write Protect Pin for Hardware Data Protection
- Utilizes Different Array Protection Compared to the AT24C02/04/08/16
* Medium-voltage and Standard-voltage Operation * * * * * * * * * * *
- 5.0 (VCC = 4.5V to 5.5V) - 2.7 (VCC = 2.7V to 5.5V) Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 400 kHz (2.7V, 5V) Clock Rate 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms Max) High Reliability - Endurance: One Million Write Cycles - Data Retention: 100 Years Automotive Grade, Extended Temperature, and Lead-Free/Halogen-Free Devices Available 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Two-wire Serial EEPROM Extended Temperature
2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) 16K (2048 x 8)
Description
The AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT24C02A/04A/08A/16A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) version. Table 1. Pin Configurations
Pin Name A0-A2 SDA SCL WP NC Function Address Inputs Serial Data Serial Clock Input Write Protect No-connect
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA A0 A1 A2 GND
8-lead PDIP
1 2 3 4 8 7 6 5 VCC WP SCL SDA
AT24C02A AT24C04A AT24C08A AT24C16A
8-lead SOIC
8-lead TSSOP
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
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Absolute Maximum Ratings*
Operating Temperature......................................-40C to +125C Storage Temperature .........................................-65C to +150C Voltage on Any Pin with Respect to Ground ........................................ -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
START STOP LOGIC
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or opencollector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under Device Addressing, page 9). The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
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The AT24C08A only uses the A2 input for hardwire addressing, and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are noconnects. The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects. WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a WP pin that provides hardware data protection. The WP pin allows normal read/write operations when connected to ground (GND). When the WP pin is connected to VCC, the write protection feature is enabled and operates as shown. (See Table 1.) Table 1. Write Protect
Part of the Array Protected WP Pin Status At VCC At GND 24C02A Upper Half (1K) Array 24C04A Upper Half (2K) Array 24C08A Full (8K) Array 24C16A Full (16K) Array
Normal Read/Write Operations
Memory Organization
AT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8 bytes each. Random word addressing requires an 8-bit data word address. AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16 bytes each. Random word addressing requires a 9-bit data word address. AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16 bytes each. Random word addressing requires a 10-bit data word address. AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of 16 bytes each. Random word addressing requires an 11-bit data word address.
Table 2. Pin Capacitance Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, Vcc= +2.7V
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
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Table 3. DC Characteristics Applicable over recommended operating range from: TAE = -40C to +125C, VCC = +2.7V to +5.5V (unless otherwise noted)
Symbol VCC3 ICC ICC ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level (1) Input High Level
(1)
Test Condition
Min 2.7
Typ
Max 5.5
Units V mA mA A A A A V V V V
READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = V CC or VSS -0.6 VCC x 0.7 IOL = 2.1 mA IOL = 0.15 mA
0.4 2.0 1.6 8.0 0.10 0.05
1.0 3.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2
Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V
1. VIL min and VIH max are reference only and are not tested.
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Table 4. AC Characteristics Applicable over recommended operating range from TAE = -40C to +125C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
AT24C02A/04A/08A/16A Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance Note:
(2)
Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time
(1)
Min
Max 400
Units kHz s s
1.2 0.6 50 0.1 1.2 0.6 0.6 0 100 300 300 0.6 50 5 1M 0.9
ns s s s s s ns ns ns s ns ms Write Cycles
Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(2) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time(2) Inputs Fall Time
(2)
Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Page Mode
1. This parameter is characterized and is not 100% tested (TA = 25C). 2. This parameter is characterized and is not 100% tested.
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Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined in Figure 2. Figure 2. Data Validity
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other command (see Figure 3). Figure 3. Start and Stop Definition
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode that is enabled (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.
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MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition as SDA is high. Figure 4. Bus Timing
Figure 5. Write Cycle Timing
SCL
SDA
8th BIT
ACK
WORDn twr STOP CONDITION
Note:
(1)
START CONDITION
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle.
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Figure 6. Output Acknowledge
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Device Addressing
The 2K, 4K, and 8K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in Figure 7. Figure 7. Device Address
2K 1 MSB 4K 1 0 1 0 0 1 0 A2 A1 A0 R/W LSB A2 A1 P0 R/W A2 P1 P0 R/W P2 P1 P0 R/W
8K
1
0
1
0
16K
1
0
1
0
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next three bits are the A2, A1, and A0 device address bits for the 2K EEPROM. These three bits must compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no-connect. The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing. The A2 bit must compare to its corresponding hardwired input pin. The A1 and A0 pins are no-connect. The 16K EEPROM does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no-connects. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high, and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgement. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time, the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle, and the EEPROM will not respond until the write is complete, as shown in Figure 8.
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Figure 8. Byte Write
S T A R T SDA LINE M S B LRA S/C BW K M S B L S B A C K A C K W R I T E S T O P
DEVICE ADDRESS
WORD ADDRESS
DATA
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K, and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition, as shown in Figure 9. Figure 9. Page Write
S T A R T SDA LINE M S B LR A S/ C BW K A C K A C K A C K A C K W R I T E WORD ADDRESS (n) S T O P
DEVICE ADDRESS
DATA (n)
DATA (n + 1)
DATA (n + x)
The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0" allowing the read or write sequence to continue.
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Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition, as shown in Figure 10. Figure 10. Current Address Read
S T A R T SDA LINE M S B LR A S/ C BW K DATA N O A C K R E A D S T O P
DEVICE ADDRESS
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition, as shown in Figure 11. Figure 11. Random Read
S T A R T SDA LINE M S B LR A S/ C BW K M S B LA SC BK M S B L S B A C K DATA n N O A C K W R I T E S T A R T DEVICE ADDRESS R E A D S T O P
DEVICE ADDRESS
WORD ADDRESS n
DUMMY WRITE
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the
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microcontroller does not respond with a "0" but does generate a following stop condition, as shown in Figure 12. Figure 12. Sequential Read
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AT24C02A Ordering Information
Ordering Code AT24C02A-10PE-2.7 AT24C02AN-10SE-2.7 AT24C02A-10PQ-2.7 AT24C02AN-10SQ-2.7 AT24C02A-10TQ-2.7 Note: Package 8P3 8S1 8P3 8S1 8A2 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free/ Extended Temperature (-40C to 125C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).
Package Type 8P3 8S1 8A2 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
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AT24C04A Ordering Information
Ordering Code AT24C04A-10PE-2.7 AT24C04AN-10SE-2.7 AT24C04A-10TE-2.7 AT24C04A-10PQ-2.7 AT24C04A-10TQ-2.7 AT24C04AN-10SQ-2.7 Note: Package 8P3 8S1 8A2 8P3 8A2 8S1 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free Extended Temperature (-40C to 125C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).
Package Type 8P3 8S1 8A2 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
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AT24C08A Ordering Information
Ordering Code AT24C08A-10PE-2.7 AT24C08AN-10SE-2.7 AT24C08A-10PQ-2.7 AT24C08AN-10SQ-2.7 AT24C08AN-10TQ-2.7 Note: Package 8P3 8S1 8P3 8S1 8A2 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free/ Extended Temperature (-40C to 125C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 3 on page 4 and Table 4 on page 5).
Package Type 8P3 8S1 8A2 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
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AT24C16A Ordering Information
Ordering Code AT24C16A-10PE-2.7 AT24C16AN-10SE-2.7 AT24C16A-10PQ-2.7 AT24C16AN-10SQ-2.7 AT24C16A-10TQ-2.7 Note: Package 8P3 8S1 8P3 8S1 8A2 Operation Range Extended Temperature (-40C to 125C) Lead-free/Halogen-free Extended Temperature (-40C to 125C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table (Table 3 on page 4 and Table 4 on page 5).
Package Type 8P3 8S1 8A2 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options -2.7 Low Voltage (2.7V to 5.5V)
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Packaging Information
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN - NOM - MAX NOTE
A A2 b b2 b3 c D
0.210 0.195 0.022 0.070 0.045 0.014 0.400
-
2
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240
0.130 0.018 0.060 0.039 0.010 0.365
-
5 6 6
3 3 4 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.310 0.250 0.100 BSC 0.300 BSC
0.325 0.280
Side View
4 0.150 2
0.115
0.130
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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8S1 - JEDEC SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 b C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
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8A2 - TSSOP
3
21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
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5083A-SEEPR-9/04

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